1. Field of the Invention
The present invention relates to a semiconductor device including a semiconductor substrate having metal wires and electrodes each formed thereon, and a manufacturing method of the semiconductor device.
2. Description of the Related Art
Along with development of highly integrated, fine semiconductor elements, recently, element electrodes increase in number and a semiconductor integrated circuit including plural semiconductor elements reduces in size at a rapid pace. As a result, an element electrode to be formed on a semiconductor integrated circuit on a semiconductor substrate requires a finer pitch and a reduction in area. In order to respond to the demands, however, it is indispensable that a probe directly coming into contact with an element electrode in an electrical characteristic test is improved and a technique for fine patterning such as wire bonding is developed. Consequently, it is difficult to respond to the aforementioned demands rapidly under current circumstances. As one of solutions, there is developed a rewiring technique that electrodes for external connection are provided on a semiconductor substrate in a lattice shape and element electrodes arranged on a periphery are connected to each other through a metal wire. According to the rewiring technique, it is possible to respond to the demands of a finer pitch and a reduction in area in regard to element electrodes arranged on a periphery and to increase element electrodes in number. Examples of a typical semiconductor package using the rewiring technique include a FC-BGA (Flip Chip Ball Grid Array) that a bump electrode is formed on an electrode for external connection and is connected to an interface substrate by a flip chip connection, and a wafer level CSP (Chip Size Package) that an external terminal is directly formed on an electrode for external connection.
Herein, description will be given of terminal interconnection in a conventional wafer level CSP with reference to FIGS. 4A to 4C. FIG. 4A is a perspective view illustrating an entire semiconductor wafer. FIG. 4B is a conceptual plan view illustrating a structure of a conventional wafer level CSP. FIG. 4C is a sectional view illustrating terminal interconnection in the conventional wafer level CSP, taken along a line A-A′ in FIG. 4B.
As illustrated in FIG. 4A, chips are formed over a semiconductor wafer 106. For each chip, herein, a wafer level CSP 107 is formed as a semiconductor integrated circuit.
As illustrated in FIG. 4B, the wafer level CSP 107 includes a semiconductor substrate 101, an insulating layer 103, plural electrodes 105 for external connection, and a metal wire 104. The insulating layer 103 is provided on a side, where a semiconductor integrated circuit is formed, of the semiconductor substrate 101. Each electrode 105 for external connection transmits/receives a signal to/from an external device. The metal wire 104 connects between the electrode 105 for external connection and an element electrode 102. A material for the metal wire 104 is equal to that for the electrode 105 for external connection, and specific examples thereof include Al and Cu. Herein, processing until formation of the metal wire 104 is collectively called a rewiring technique.
As illustrated in FIG. 4C, the element electrode 102, a passivation film 108 and the insulating film 103 are formed on the semiconductor substrate 101. The element electrode 102 is connected to the semiconductor integrated circuit, and the passivation film 108 and the insulating layer 103 are partly opened at the element electrode 102.
Hereinafter, description will be given of a manufacturing method of the wafer level CSP 107 with reference to FIGS. 4A to 4C.
First, an element electrode 102 and a passivation film 108 are formed on a semiconductor substrate 101. Then, an insulating layer 103 is deposited over a surface of the semiconductor substrate 101 by a spin coating method. Thereafter, an opening 103a is formed in the insulating layer 103 by a well-known lithography technique so that the element electrode 102 is exposed therefrom. Next, a Cu film is deposited on the insulating layer 103 by a sputtering method or the like. Then, the Cu film is selectively etched. Thus, a Cu metal wire 104 for connecting between an electrode 105 for external connection, transmitting/receiving a signal to/from an external device, and the element electrode 102 is formed on the insulating layer 103.
Conventionally, a TEG (Test Element Group) wafer for process evaluation, different from a product wafer, is used for evaluating and analyzing a degree of reliability in a metal wire 104, determining process conditions of a rewiring technique, and introducing the determined process conditions into an actual manufacturing process of a product wafer. Herein, a metal wire 104 is subjected to evaluation by an electrical test in regard to reliability in wiring such as an open failure, a short-circuit failure and a leakage failure and reliability in connectivity with an element electrode 102. In a wafer level CSP 107, further, a product wafer having a design rule equal to that of a TEG wafer for process evaluation, such as a width and an interval (hereinafter, referred to as “Line/Space”) of a metal wire 104, a pitch between electrodes 105 for external connection, and a dimension of an opening 103a on an element electrode 102, adopts process conditions equal to those in the TEG wafer for process evaluation, and is not subjected to evaluation by an electrical test in regard to reliability in wiring of the metal wire 104 such as an open failure, a short-circuit failure and a leakage failure and reliability in connectivity between the metal wire 104 and the element electrode 102 in general. Actually, a wiring state of a metal wire 104 in a product wafer is visually checked or is checked by an automatic appearance test during a manufacturing process. Further, after completion, a wafer level CSP is subjected to a final electrical characteristic test in order to inspect an open failure, a short-circuit failure and an leakage failure that cannot be checked by an appearance test, and connectivity between an element electrode 102 and a metal wire 104. Upon detection of a failure, a product having the failure is subjected to polishing or failure analysis using a FIB (Focused Ion Beam) or a SEM (Scanning Electron Microscope) in order to identify whether a defective site is a semiconductor integrated circuit or a metal wire.
As described above, a product wafer having a design rule equal to that of a TEG wafer for process evaluation, such as Line/Space of a metal wire, a pitch between electrodes for external connection, and a dimension of an opening on an element electrode adopts process conditions determined for the TEG wafer for process evaluation and, therefore, is not actually subjected to evaluation by an electrical test for a metal wire performed for the TEG wafer for process evaluation. However, a TEG wafer for process evaluation is different from a product wafer in internal wiring design and pattern dimension of a semiconductor substrate. Therefore, the TEG wafer for process evaluation is largely different from the product wafer in surface irregularities of a semiconductor substrate. In some cases, such surface irregularities of the semiconductor substrate affect reliability of a metal wire to be formed on the semiconductor substrate. Further, a surface state of an element electrode, more specifically, a state of a surface coat of an element electrode differs for each product wafer; therefore, reliability in connectivity between an element electrode and a metal wire also differs for each product wafer. In some cases, reliability of a metal wire cannot be secured with certainty. In addition, a conventional appearance test method has limitations in regard to detection precision. Therefore, as a metal wire is formed finely, it is difficult to accurately detect a shape failure of a metal wire, resulting in an outflow of defective products with a high possibility. Such a defective product must be detected in a final electrical characteristic test. Further, even when a defective product is detected in a final electrical characteristic test, such a defective product must be subjected to polishing or processing using a FIB in order to identify whether a defective site is a semiconductor integrated circuit or a metal wire and, further, is subjected to failure analysis by observation using a SEM or the like. Therefore, it takes much time to obtain a result of the analysis, and it is difficult to feed back the result to subsequent lots in a timely manner. Moreover, a product wafer is subjected to a test in a complete state; therefore, it is impossible to replace a defective wafer or chip with new one.